Nanoelectronics:

Introduction:

The use of nanotechnology to electronic components is known as nanoelectronics. The fact that they are so small necessitates a thorough understanding of interatomic interactions and quantum mechanical features, which unites the term's varied range of devices and materials. These contenders include sophisticated molecular electronics, one-dimensional nanotubes or nanowires (such as silicon or carbon nanowires), and hybrid molecular and semiconductor electronics.

 

Nanoelectronics

Critical dimensions for nanoelectronic devices range from 1 nm to 100 nm in size. The 22 nanometer CMOS (complementary MOS) node and succeeding 14 nm, 10 nm, and 7 nm FinFET (fin field-effect transistor) generations are recent silicon MOSFET (metal-oxide-semiconductor field-effect transistor, or MOS transistor) technological generations that are already within this domain. Because the contenders currently under consideration differ greatly from conventional transistors, nanoelectronics is occasionally referred to as a disruptive technology.

 

Gordon Moore noticed that silicon transistors were continuously scaling down in 1965; this observation later became known as Moore's law. As of 2019, transistor minimum feature sizes have dropped from 10 micrometres to a range of 10 nanometers since his observation. Note that the minimum feature size is not a straight representation of the technology node. By utilising novel techniques and materials to create electrical devices with nanoscale feature sizes, the discipline of nanoelectronics seeks to facilitate the continuous implementation of this law.

 

History:

A. Rose developed and demonstrated metal nanolayer-base transistors in 1960, while Atalla, Kahng, and Geppert did the same in 1962. Geppert, Atalla, and Kahng created the first nanolayer-base metal-semiconductor junction transistor in 1962 using gold (Au) thin films with a 10 nm thickness. A metal-oxide-semiconductor field-effect transistor (MOSFET) with a 10 nm gate oxide thickness was demonstrated in 1987 by an IBM research team under the direction of Bijan Davari.

 

Beginning with the FinFET (fin field-effect transistor), a three-dimensional, non-planar, double-gate MOSFET, multi-gate MOSFETs allowed scaling down 20 nm gate length. The DELTA transistor was created in 1989 by Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, and Eiji Takeda at Hitachi Central Research Laboratory. A research team at UC Berkeley was given a contract by DARPA in 1997 to create a deep sub-micron DELTA transistor. The team included Hisamoto, Chenming Hu from TSMC, Tsu-Jae King Liu, Jeffrey Bokor, Hideki Takeuchi, K. Asano, Jakub Kedziersk, Xuejue Huang, Leland Chang, Nick Lindert, Shibly Ahmed, and Cyrus Tabery, as well as other researchers from around the world. In 1998 and 2001, the team successfully manufactured FinFET devices using processes as small as 15 nm.A group led by Yu, Chang, Ahmed, Hu, Liu, Bokor, and Tabery produced a 10 nm FinFET device in 2002.

 

A CMOS (complementary MOS) transistor created in 1999 at the Grenoble, France-based Laboratory for Electronics and Information Technology explored the limits of the MOSFET transistor's operating principles. This transistor had an 18 nm diameter (approximately 70 atoms placed side by side). Theoretically, it made it possible to fit seven billion connections onto a €1 coin. The CMOS transistor was a demonstration of how this technology works now that we are coming closer to working on a molecular scale rather than a simple research experiment to explore how CMOS technology works.According to Jean-Baptiste Waldner in 2007, it would be hard to both master and produce on an industrial scale the coordinated construction of several of these transistors on a circuit.

 

The world's smallest nanoelectronic device, a 3 nm MOSFET, was created in 2006 by a group of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center. Gate-all-around (GAA) FinFET technology served as its foundation.

 

The 2010s saw the start of commercial nanoelectronic semiconductor device manufacture. The commercial mass manufacturing of a 16 nm process by SK Hynix, a 16 nm FinFET technology by TSMC, and a 10 nm class process by Samsung Electronics all started in 2013. Samsung started producing using a 5 nm process in 2018, while TSMC started using a 7 nm process in 2017. A 3 nm process will be commercially produced by TSMC by 2022, according to plans made public in 2017. Samsung stated in 2019 that it would implement a 3 nm GAAFET (gate-all-around FET) technique by 2021.